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single channel, 16-bit, serial input, current source & voltage output dac preliminary technical data AD5422 rev. pre information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features 16-bit resolution and monotonicity current output ranges: 4C20ma, 0C20ma or 0C24ma 0.1% typ total unadjusted error (tue) 5ppm/c output drift voltage output ranges: 0-5v, 0-10v, 5v, 10v, 10% over-range 0.05% total unadjusted error (tue) 3ppm/c output drift flexible serial digital interface on-chip output fault detection on-chip reference (10 ppm/c max) asynchronous clear function power supply range av dd : 10.8v to 40 v av ss : -26.4v to -3v/0v output loop compliance to av dd C 2.5 v temperature range: -40c to +85c tssop and lfcsp packages applications process control actuator control plc general description the AD5422 is a low-cost, precision, fully integrated 16-bit converter offering a programmable current source and programmable voltage output designed to meet the requirements of industrial process control applications. the output current range is programmable to 4ma to 20 ma, 0ma to 20ma or an overrange function of 0ma to 24ma. voltage output is provided from a separate pin that can be configured to provide 0v to 5v, 0v to 10v, 5v or 10v output ranges, an over-range of 10% is available on all ranges. analog outputs are short and open circuit protected and can drive capacitive loads of 1uf and inductive loads of 1h. the device is specified to operate with a power supply range from 10.8 v to 40 v. output loop compliance is 0 v to av dd ? 2.5 v. the flexible serial interface is spi and microwire compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. the device also includes a power-on-reset function ensuring that the device powers up in a known state and an asynchronous clear pin which sets the outputs to zero-scale / mid-scale voltage output or the low end of the selected current range. the total output error is typically 0.1% in current mode and 0.05% in voltage mode. table 1. related devices part number description ad5412 single channel, 12-bit, serial input current source and voltage output dac ad5420 single channel, 16-bit, serial input current source dac ad5410 single channel, 12-bit, serial input current source dac
AD5422 preliminary technical data rev. pre | page 2 of 37 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications..................................................................................... 4 ac performance characteristics ................................................ 7 timing characteristics ................................................................ 8 absolute maximum ratings.......................................................... 10 esd caution................................................................................ 10 pin configuration and function descriptions........................... 11 typical performance characteristics voltage output ............... 13 typical performance characteristics current output ............... 17 typical performance characteristics general ............................ 20 terminology .................................................................................... 22 theory of operation ...................................................................... 24 architecture................................................................................. 24 serial interface ............................................................................ 24 default configuration................................................................. 28 transfer function ....................................................................... 28 data register ............................................................................... 29 control register.......................................................................... 29 reset register ............................................................................ 29 status register .............................................................................. 30 features ............................................................................................ 31 fault alert...................................................................................... 31 voltage output short circuit protection.................................... 31 asynchronous clear (clear) ................................................. 31 internal reference ...................................................................... 31 external current setting resistor............................................... 31 voltage output over-range........................................................ 31 digital power supply.................................................................. 31 external boost function............................................................. 31 digital slew rate control ............................................................. 32 i out filtering capacitors ............................................................ 32 applications information .............................................................. 33 driving inductive loads .............................................................. 33 transient voltage protection ..................................................... 33 layout guidelines....................................................................... 33 galvanically isolated interface ................................................. 33 microprocessor interfacing....................................................... 33 thermal and supply considerations......................................... 34 outline dimensions ....................................................................... 35 ordering guide .......................................................................... 35 revision history pre C preliminary version, november 22, 2007
preliminary technical data AD5422 rev. pre | page 3 of 37 functional block diagram vref 16-bit dac input shift register and control logic r1 r2 r3 v out i out range scaling latch sclk sdin sdo dv cc agnd clear fault power on reset boost av ss av dd refout refin +v sense -v sense clear select r set / 16 dv cc select AD5422 c comp2 c comp1 cap1 cap2 dgnd* *lfcsp package figure 1.
AD5422 preliminary technical data rev. pre | page 4 of 37 specifications av dd = 10.8v to 40v, av ss = -26.4v to -3v/0v, av dd + |av ss | < 52.8v, agnd = dgnd = 0 v, refin= +5 v external; dv cc = 2.7 v to 5.5 v, v out : r l = 2 k?, c l = 200 pf, i out : r l = 300 ? , h l = 50mh; all specifications t min to t max , 10 v / 0 to 24 ma range unless otherwise noted. table 2. parameter value 1 unit test conditions/comments voltage output output voltage ranges 0 to 5 v 0 to 10 v -5 to +5 v -10 to +10 v accuracy output unloaded bipolar output resolution 16 bits total unadjusted error (tue) 0.1 % fsr max over temperature, supplies, and time, typically 0.05% fsr tue tc 2 3 ppm typ relative accuracy (inl) 0.012 % fsr max differential nonlinearity (dnl) 1 lsb max guaranteed monotonic bipolar zero error 5 mv max @ 25c, error at other temperatures obtained using bipolar zero tc bipolar zero tc 2 3 ppm fsr/c max zero-scale error 1 mv max @ 25c, error at other temperatures obtained using zero scale tc zero-scale tc 2 3 ppm fsr/c max gain error 0.05 % fsr max @ 25c, error at other temperatures obtained using gain tc gain tc 2 8 ppm fsr/c max full-scale error 0.05 % fsr max @ 25c, error at other temperatures obtained using gain tc full-scale tc 2 3 ppm fsr/c max unipolar output av ss = 0 v resolution 16 bits total unadjusted error (tue) 0.1 % fsr max over temperature, supplies, and time, typically 0.05% fsr relative accuracy (inl) 0.012 % fsr max differential nonlinearity (dnl) 1 lsb max guaranteed monotonic (at 16 bit-resolution) zero scale error +10 mv max @ 25c, error at other temperatures obtained using gain tc zero scale tc 2 3 ppm fsr/c max offset error 10 mv max gain error 0.05 % fsr max @ 25c, error at other temperatures obtained using gain tc gain tc 2 3 ppm fsr/c max full-scale error 0.05 % fsr max @ 25c, error at other temperatures obtained using gain tc full-scale tc 2 3 ppm fsr/c max output characteristics 2 headroom 0.8 v max 0.5 v typ output voltage tc 3 ppm fsr/c max output voltage drift vs. time 12 ppm fsr/500 hr typ vout = ? of full-scale 15 ppm fsr/1000 hr typ short-circuit current 12 ma typ
preliminary technical data AD5422 rev. pre | page 5 of 37 parameter value 1 unit test conditions/comments load 2 k? min for specified performance capacitive load stability r l = 20 nf max r l = 2 k? tbd nf max r l = 1 f max external compensation capacitor of 4nf connected. dc output impedance 0.3 ? typ power-on time 10 s typ dc psrr tbd v/v current output output current ranges 0 to 24 ma 0 to 20 ma 4 to 20 ma accuracy resolution 16 bits total unadjusted error (tue) 0.3 % fsr max over te mperature, supplies, and time, typically 0.1% fsr tue tc 2 5 ppm/c typ relative accuracy (inl) 0.012 % fsr max differential nonlinearity (dnl) 1 lsb max guaranteed monotonic offset error 0.05 % fsr max offset error drift 5 v/c typ gain error 0.02 % fsr max @ 25c, error at other temperatures obtained using gain tc gain tc 2 8 ppm fsr/c max full-scale error 0.05 % fsr max @ 25c, error at other temperatures obtained using gain tc full-scale tc 2 8 ppm fsr/c output characteristics 2 current loop compliance voltage avdd - 2.5 v max output current drift vs. time tbd ppm fsr/500 hr typ tbd ppm fsr/1000 hr typ resistive load tbd ? max inductive load 1 h max dc psrr 10 a/v max output impedance 50 m? typ reference input/output reference input 2 reference input voltage 5 v nom 1% for specified performance dc input impedance 30 k? min typically 40 k? reference range 4 to 5 v min to v max reference output output voltage 4.998 to 5.002 v min to v max @ 25c reference tc 10 ppm/c max output noise (0.1 hz to 10 hz) 2 18 v p-p typ noise spectral density 2 120 nv/hz typ @ 10 khz output voltage drift vs. time 2 40 ppm/500 hr typ 50 ppm/1000 hr typ capacitive load tbd nf max load current 5 ma typ short circuit current 7 ma typ line regulation 2 10 ppm/v typ load regulation 2 tbd ppm/ma thermal hysteresis 2 tbd ppm
AD5422 preliminary technical data rev. pre | page 6 of 37 parameter value 1 unit test conditions/comments digital inputs 2 dv cc = 2.7 v to 5.5 v, jedec compliant v ih , input high voltage 2 v min v il , input low voltage 0.8 v max input current 1 a max per pin pin capacitance 10 pf typ per pin digital outputs 2 sdo v ol , output low voltage 0.4 v max sinking 200 a v oh , output high voltage dv cc ? 0.5 v min sourcing 200 a high impedance leakage current 1 a max high impedance output capacitance 5 pf typ fault v ol , output low voltage 0.4 v max 10k ? pull-up resistor to dv cc v ol , output low voltage 0.6 v typ @ 2.5 ma v oh , output high voltage 3.6 v min 10k ? pull-up resistor to dv cc power requirements av dd 10.8 to 40 v min to v max av ss -26.4 to 0 v min to v max dv cc input voltage 2.7 to 5.5 v min to v max internal supply disabled output voltage 4.5 v typ dv cc can be overdriven up to 5.5v output load current 5 ma typ short circuit current 20 ma typ ai dd tbd ma output unloaded ai ss tbd ma output unloaded di cc 1 ma max v ih = dv cc , v il = gnd, tbd ma typ power dissipation tbd mw typ av dd = 40v, av ss = 0 v, v out unloaded tbd mw typ av dd = 40v, av ss = -15 v, v out unloaded tbd mw typ av dd = 15v, av ss = -15 v, v out unloaded 1 temperature range: -40c to +85c; typical at +25c. 2 guaranteed by characterization. not production tested.
preliminary technical data AD5422 rev. pre | page 7 of 37 ac performance characteristics av dd = 10.8v to 40v, av ss = -26.4v to -3v/0v, av dd + |av ss | < 52.8v, agnd = dgnd = 0 v, refin= +5 v external; dv cc = 2.7 v to 5.5 v, v out : r l = 2 k?, c l = 200 pf, i out : r l = 300 ? , h l = 50mh; all specifications t min to t max , 10 v / 0 to 24 ma range unless otherwise noted. table 3. parameter 1 unit test conditions/comments dynamic performance voltage output output voltage settling time 8 s typ full-scale step (10 v) to 0.03% fsr 10 s max 5 s max 512 lsb step settling output current settling time 10 s max to 0.1% fsr slew rate 1 v/s typ power-on glitch energy 10 nv-sec typ digital-to-analog glitch energy 10 nv-sec typ glitch impulse peak amplitude 20 mv typ digital feedthrough 1 nv-sec typ output noise (0.1 hz to 10 hz bandwidth) 0.1 lsb p-p typ output noise (100 khz bandwidth) 80 v rms max 1/f corner frequency 1 khz typ output noise spectral density 100 nv/hz typ measured at 10 khz ac psrr tbd db 200mv 50/60hz sinewave superimposed on power supply voltage. current output output current settling time tbd s typ to 0.1% fsr , l = 1h tbd s typ to 0.1% fsr , l < 1mh 1 guaranteed by characterization, not production tested.
AD5422 preliminary technical data rev. pre | page 8 of 37 timing characteristics av dd = 10.8v to 40v, av ss = -26.4v to -3v/0v, av dd + |av ss | < 52.8v, agnd = dgnd = 0 v, refin= +5 v external; dv cc = 2.7 v to 5.5 v, v out : r l = 2 k?, c l = 200 pf, i out : r l = 300 ? , h l = 50mh; all specifications t min to t max , 10 v / 0 to 24 ma range unless otherwise noted. table 4. parameter 1, 2, 3 limit at t min , t max unit description write mode t 1 33 ns min sclk cycle time t 2 13 ns min sclk low time t 3 13 ns min sclk high time t 4 13 ns min latch delay time t 5 40 ns min latch high time t 5 5 s min latch high time (after a write to the control register) t 6 5 ns min data setup time t 7 5 ns min data hold time t 8 40 ns min latch low time t 9 20 ns min clear pulsewidth t 10 5 s max clear activation time readback mode t 11 82 ns min sclk cycle time t 12 33 ns min sclk low time t 13 33 ns min sclk high time t 14 13 ns min latch delay time t 15 40 ns min latch high time t 16 5 ns min data setup time t 17 5 ns min data hold time t 18 40 ns min latch low time t 19 40 ns max serial output delay time (c l sdo 4 = 15pf) t 20 33 ns max latch rising edge to sdo tri-state daisychain mode t 21 82 ns min sclk cycle time t 22 33 ns min sclk low time t 23 33 ns min sclk high time t 24 13 ns min latch delay time t 25 40 ns min latch high time t 26 5 ns min data setup time t 27 5 ns min data hold time t 28 40 ns min latch low time t 29 40 ns max serial output delay time (c l sdo 4 = 15pf) 1 guaranteed by characterization. not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 3 see figure 2, figure 3, and figure 4. 4 c l sdo = capacitive load on sdo output.
preliminary technical data AD5422 rev. pre | page 9 of 37 db23 sclk latch sdin 24 2 1 db0 t 7 t 6 t 2 t 3 t 1 t 4 clear output t 10 t 9 t 5 t 8 figure 2. write mode timing diagram db23 sclk latch sdin 24 2 1 db0 t 17 t 16 t 12 t 13 t 11 t 14 t 15 t 18 sdo t 19 db23 selected register data clocked out nop condition undefined data input word specifies register to be read 1 2 24 db0 db15 db0 x x x x 8 923 22 first 8 bits are don?t care bits t 20 figure 3. readback mode timing diagram db23 sclk sdin 24 2 1 db0 t 27 t 26 sdo db23 db0 t 29 db23 db0 input word for dac n input word for dac n-1 undefined input word for dac n 25 48 26 latch t 22 t 23 t 21 t 24 t 25 t 28 db23 db0 figure 4. daisychain mode timing diagram
AD5422 preliminary technical data rev. pre | page 10 of 37 absolute maximum ratings t a = 25c unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 5. parameter rating av dd to agnd, dgnd ?0.3v to 48v av ss to agnd, dgnd +0.3 v to ?48 v av dd to av ss -0.3v to 60v dv cc to agnd, dgnd ?0.3 v to +7 v digital inputs to agnd, dgnd ?0.3 v to dv cc + 0.3 v or 7 v (whichever is less) digital outputs to agnd, dgnd ?0.3 v to dv cc + 0.3 v or 7v (whichever is less) refin/refout to agnd, dgnd ?0.3 v to +7 v v out to agnd, dgnd av ss to av dd i out to agnd, dgnd ?0.3v to av dd agnd to dgnd -0.3v to +0.3v operating temperature range industrial ?40c to +85 1 c storage temperature range ?65c to +150c junction temperature (t j max) 125c 24-lead tssop package ja thermal impedance 42c/w 40-lead lfcsp package ja thermal impedance 28c/w power dissipation (t j max C t a )/ ja lead temperature jedec industry standard soldering j-std-020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 power dissipated on chip must be de-rated to keep junction temperature below 125c. assumption is max powe r dissipation condition is sourcing 24ma into ground from av dd with a 3ma on-chip current.
preliminary technical data AD5422 rev. pre | page 11 of 37 pin configuration and fu nction descriptions 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 AD5422 agnd sdo av ss +v sense fault gnd latch clear clear select refin selec t sclk sdin gnd r set v out boost c comp1 refout top view (not to scale) dv cc c comp2 i out -v sense av dd dv cc 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 40 39 38 37 36 35 34 33 32 31 dgnd gnd av ss nc latch clear select av ss av dd nc gnd fault nc nc -v sense dv cc nc nc dv cc select +v sens e v out boost c comp1 c comp2 i out nc sdo sdin sclk nc r set nc agnd clear nc top view (not to scale) AD5422 nc nc refin refout cap2 cap1 figure 5. tssop pin configuration figure 6. lfcsp pin configuration table 6. pin function descriptions tssop pin no. lfcsp pin no. mnemonic description 1 14,37 av ss negative analog supply pin. voltage ranges from C3 v to C24 v. this pin can be connected to 0v if output voltage range is unipolar. 2 39 dv cc digital supply pin. voltage ranges from 2.7 v to 5.5 v. 3 2 fault fault alert, this pin is asserted low when an open circuit is detected in current mode or an over temperature is detected. open drain output, must be connected to a pull-up resistor. 4,12 3,15 gnd these pins must be connected to 0v. 1,10,11,19, 20,21,22,30, 31,35,38,40 nc no connection. 5 4 clear select selects the voltage output clear value, either zero-scale or mid-scale code. see table 20 6 5 clear active high input. asserting this pin will set the current output to the bottom of the selected range or will set the voltage output to the user selected value (zero-scale or mid-scale). 7 6 latch positive edge sensitive latch, a rising edge will parallel load the input shift register data into the dac register, also updating the output. 8 7 sclk serial clock input. data is cloc ked into the shift register on the rising edge of sclk. this operates at clock speeds up to 30 mhz. 9 8 sdin serial data input. data must be valid on the rising edge of sclk. 10 9 sdo serial data output. used to cl ock data from the serial register in daisy-chain or readback mode. data is clocked out on the falling ed ge of sclk . see figure 3 and figure 4. 11 12 agnd ground reference pin for analog circuitry. n/a 13 dgnd ground reference pin for digital circuitry. (agnd and dgnd are internally connected in tssop package). 13 16 r set an external, precision, low drift 15k ? current setting resistor can be connected to this pin to improve the i out temperature drift performance. refer to features section. 14 17 refout internal reference voltage output. refout = 5 v 2 mv. 15 18 refin external reference voltage input. reference input range is 4 v to 5 v. refin = 5 v for specified performance. 16 23 dv cc select this pin when connected to gnd disables the internal supply and an external supply must be connected to the dv cc pin. leave this pin unconnected to enable the internal supply. refer to features section. 17 24 c comp1 18 25 c comp2 optional compensation capacitor connectio n for the voltage output buffer. connecting a 4nf capacitor between these pins will allow the voltage output to drive up to 1f.
AD5422 preliminary technical data rev. pre | page 12 of 37 tssop pin no. lfcsp pin no. mnemonic description 19 26 i out current output pin. 20 27 boost optional external transistor connection. conne cting an external transistor will reduce the power dissipated in the AD5422. refer to the features section. n/a 28 cap1 connection for optional output filter ing capacitor. refer to features section. n/a 29 cap2 connection for optional output filter ing capacitor. refer to features section. 21 32 v out buffered analog output voltage. the output amplifier is capable of directly driving a 2 k?, 2000 pf load. 22 33 +v sense sense connection for the positive voltage output load connection. 23 34 -v sense sense connection for the negative voltage output load connection. 24 36 av dd positive analog supply pin. voltage ranges from 10.8v to 60v. paddle paddle av ss negative analog supply pin. voltage ranges from C3 v to C24 v. this pin can be connected to 0v if output voltage range is unipolar.
preliminary technical data AD5422 rev. pre | page 13 of 37 typical performance characteristics voltage output figure 7. integral non linearity error vs dac code (four traces) figure 8. differential non linearity error vs. dac code (four traces) figure 9. total unadjusted error vs. dac code (four traces) figure 10. integral non linearity vs. temperature (four traces) figure 11. differential non linearity vs. temperature (four traces) figure 12. integral non linearity vs. supply voltage (four traces)
AD5422 preliminary technical data rev. pre | page 14 of 37 figure 13.differential non linearity error vs. supply voltage (four traces) figure 14. integral non linearity error vs. reference voltage (four traces) figure 15. differential non linearity er ror vs. reference voltage (four traces) figure 16. total unadjusted error vs.reference voltage (four traces) figure 17. total unadjusted error vs. supply voltage (four traces) figure 18. offset error vs.temperature
preliminary technical data AD5422 rev. pre | page 15 of 37 figure 19. bipolar zero error vs. temperature figure 20. gain error vs. temperature figure 21. source and sink capability of output amplifier full-scale code loaded figure 22. source and sink capability of output amplifier zero-scale loaded figure 23.full-scale positive step figure 24. full-scale negative step
AD5422 preliminary technical data rev. pre | page 16 of 37 figure 25. digital-to-analog glitch energy figure 26. peak-to-peak noise (0.1hz to 10hz bandwidth) figure 27. peak-to-peak noise (100khz bandwidth) figure 28. v out vs. time on power-up figure 29. v out vs, time on output enabled
preliminary technical data AD5422 rev. pre | page 17 of 37 typical performance characteristics current output figure 30. integral non linearity vs. code figure 31.differential non linearity vs. code figure 32. total unadjusted error vs. code figure 33. integral non linearity vs. temperature figure 34. differential non linearity vs. temperature figure 35. integral non linearity vs. supply
AD5422 preliminary technical data rev. pre | page 18 of 37 figure 36. differential non linearity vs. supply voltage figure 37. integral non linearity vs. reference voltage figure 38. differential non li nearity vs. reference voltage figure 39. total unadjusted error vs. reference voltage figure 40. total unadjusted error vs. supply voltage figure 41. offset error vs. temperature
preliminary technical data AD5422 rev. pre | page 19 of 37 figure 42. gain error vs. temperature figure 43. voltage compliance vs. temperature figure 44. i out vs. time on power-up figure 45. i out vs. time on output enabled
AD5422 preliminary technical data rev. pre | page 20 of 37 typical performance characteristics general figure 46. di cc vs.logic input voltage figure 47. ai dd /ai ss vs av dd /av ss figure 48. ai dd vs av dd figure 49. dv cc output voltage vs. di cc load current figure 50. refout turn-on transient figure 51. refout output noise (0.1hz to 10hz bandwidth)
preliminary technical data AD5422 rev. pre | page 21 of 37 figure 52. refout output noise (100khz bandwidth) figure 53. refout line transient figure 54. refout load transient figure 55. refout histogra m of thermal hysteresis figure 56. refout voltage vs. load current
AD5422 preliminary technical data rev. pre | page 22 of 37 terminology relative accuracy or integral nonlinearity (inl) for the dac, relative accuracy, or integral nonlinearity (inl), is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 7. differential nonlinearity (dnl) differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 10. monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital input code. the ad5724r/ ad5734r/ad5754r are monotonic over their full operating temperature range. bipolar zero error bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 v when the dac register is loaded with 0x8000 (straight binary coding) or 0x0000 (twos complement coding). a plot of bipolar zero error vs. temperature can be seen in table tbd. bipolar zero tc bipolar zero tc is a measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. full-scale error full-scale error is a measure of the output error when full-scale code is loaded to the dac register. ideally, the output should be full-scale ? 1 lsb. full-scale error is expressed in percent of full-scale range (% fsr). negative full-scale error/zero-scale error negative full-scale error is the error in the dac output voltage when 0x0000 (straight binary coding) or 0x8000 (twos complement coding) is loaded to the dac register. ideally, the output voltage should be negative full-scale ? 1 lsb. a plot of zero-scale error vs. temperature can be seen in table tbd zero-scale tc this is a measure of the change in zero-scale error with a change in temperature. zero-scale error tc is expressed in ppm fsr/c. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. a plot of settling time can be seen in table tbd slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed of a voltage- output d/a converter is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed in % fsr. a plot of gain error vs. temperature can be seen in table tbd gain tc this is a measure of the change in gain error with changes in temperature. gain error tc is expressed in ppm fsr/c. tot a l un a dju s te d e r ror total unadjusted error (tue) is a measure of the output error taking all the various errors into account, namely inl error, offset error, gain error, and output drift over supplies, temperature, and time. tue is expressed in % fsr. current loop voltage compliance the maximum voltage at the i out pin for which the output currnet will be equal to the programmed value. power-on glitch energy power-on glitch energy is the impulse injected into the analog output when the AD5422 is powered-on. it is specified as the area of the glitch in nv-sec. see table tbd digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state, but the output voltage remains constant. it is normally specified as the area of the glitch in nv-sec and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see table tbd glitch impulse peak amplitude glitch impulse peak amplitude is the peak amplitude of the impulse injected into the analog output when the input code in the dac register changes state. it is specified as the amplitude of the glitch in mv and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see table tbd. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-sec and measured with a full-scale code change on the data bus. power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the power supply voltage. reference tc
preliminary technical data AD5422 rev. pre | page 23 of 37 reference tc is a measure of the change in the reference output voltage with a change in temperature. it is expressed in ppm/c. line regulation line regulation is the change in reference output voltage due to a specified change in supply voltage. it is expressed in ppm/v. load regulation load regulation is the change in reference output voltage due to a specified change in load current. it is expressed in ppm/ma. thermal hysteresis thermal hysteresis is the change of reference output voltage after the device is cycled through temperatures from +25c to ?40c to +85c and back to +25c. this is a typical value from a sample of parts put through such a cycle. see table tbdfor a histogram of thermal hysteresis. tc o o hys o v v v _ _ c) 25 ( ? = 6 _ _ 10 c) 25 ( c) 25 ( ) ( ? = o tc o o hys o v v v ppm v where: v o (25c) = v o at 25c v o_tc = v o at 25c after temperature cycle
AD5422 preliminary technical data rev. pre | page 24 of 37 theory of operation the AD5422 is a precision digital to current loop and voltage output converter designed to meet the requirements of industrial process control applications. it provides a high precision, fully integrated, low cost single-chip solution for generating current loop and unipolar/bipolar voltage outputs. the current ranges available are; 0 to 20ma, 0 to 24ma and 4 to 20ma, the voltage ranges available are; 0 to 5v, 5v, 0 to 10v and 10v, the current and voltage outputs are available on separate pins and only one is active at any one time. the desired output configuration is user selectable via the control register. architecture the dac core architecture of the AD5422 consists of two matched dac sections. a simplified circuit diagram is shown in figure 57. the 4 msbs of the 16-bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects 1 of 15 matched resistors to either ground or the reference buffer output. the remaining 12 bits of the data-word drive switches s0 to s11 of a 12-bit voltage mode r-2r ladder network. 2r s0 v ref 2r s1 2r s11 2r e1 2r e2 2r e15 2r v ou t 12-bit r-2r ladder four msbs decoded into 15 equal segments rr figure 57. dac ladder structure the voltage output from the dac core is either converted to a current (see diagram, figure 58) which is then mirrored to the supply rail so that the application simply sees a current source output with respect to ground or it is buffered and scaled to output a software selectable unipolar or bipolar voltage range (see diagram, figure 59). the current and voltage are output on separate pins and cannot be output simultaneously. 16-bit dac r1 r2 r3 i out av dd a1 a2 t1 t2 figure 58. voltage to current conversion circuitry 16-bit dac v out range scaling refin v sense -v sense r l 3v r 1 figure 59. voltage output voltage output amplifier the voltage output amplifier is capable of generating both unipolar and bipolar output voltages. it is capable of driving a load of 2 k? in parallel with 1 f to agnd. the source and sink capabilities of the output amplifier can be seen in figure tbd. the slew rate is 1 v/s with a full-scale settling time of 10 s, (10v step). figure 59 shows the voltage output drving a load, r l on top of a common mode voltage of up to 3v. in output module applications where a cable could possibly become disconnected from +v sense resulting in the amplifier loop being broken and most probably resulting in large destructive voltages on v out , a resistor, r 1 , of value 2k ? to 5k ? should be included as shown to ensure the amplifier loop is kept closed. driving large capacitive loads the voltage output amplifier is capable of driving capacitive loads of up to 1uf with the addition of a non-polarised 4nf compensation capacitor between the c comp1 and c comp2 pins. without the compensation capacitor, up to 20nf capacitive loads can be driven. reference buffers the AD5422 can operate with either an external or internal reference. the reference input has an input range of 4 v to 5 v, 5 v for specified performance. this input voltage is then buffered before it is applied to the dac. serial interface the AD5422 is controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 mhz. it is compatible with spi?, qspi?, microwire?, and dsp standards. input shift register the input shift register is 24 bits wide. data is loaded into the device msb first as a 24-bit word under the control of a serial clock input, sclk. data is clocked in on the rising edge of sclk. the input register consists of 8 control bits and 16 data bits as shown in table 7. the 24 bit word is unconditionally latched on the rising edge of latch. data will continue to be clocked in irrespective of the state of latch, on the rising edge of latch the data that is present in the input register will be latched, in other words the last 24 bits to be clocked in before
preliminary technical data AD5422 rev. pre | page 25 of 37 the rising edge of latch will be the data that is latched. the timing diagram for this operation is shown in figure 2.
AD5422 preliminary technical data rev. pre | page 26 of 37 table 7. input shift register format msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 address word data word table 8. control word functions address word function 00000000 no operation (nop) 00000001 data register 00000010 readback register value as per read address (see table 10) 01010101 control register 01010110 reset register standalone operation he serial interface orks ith both a continuous and noncon- tinuous serial clock a continuous sc source can only be used if ac is taken high after the correct number of data bits hae been clocked in in gated clock mode a burst clock containing the eact number of clock cycles must be used and ac must be taken high after the final clock to latch the data he first rising edge of sc that clocks in the sb of the dataord marks the beginning ot the rite cycle actly rising clock edges must be applied to sc before ac is brought high if ac is brought high before the th rising sc edge the data ritten ill be inalid if more than rising sc edges are applied before ac is brought high the input data ill also be inalid controller data in latch sdin sclk data out serial clock control out sdo latch sclk sdo latch sclk sdo sdin sdin *additional pins omitted for clarity AD5422* AD5422* AD5422* figure 60. daisy chaining the AD5422
preliminary technical data AD5422 rev. pre | page 27 of 37 daisy-chain operation for systems that contain several devices, the sdo pin can be used to daisy chain several devices together as shown in figure 60. this daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. daisychain mode is enabled by setting the dcen bit of the control register. the first rising edge of sclk that clocks in the msb of the dataword marks the beginning of the write cycle. sclk is continuously applied to the input shift register. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the falling edge of sclk and is valid on the next rising edge. by connecting the sdo of the first device to the sdin input of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24 n , where n is the total number of AD5422 devices in the chain. when the serial transfer to all devices is complete, latch is taken high. this latches the input data in each device in the daisy chain. the serial clock can be a continuous or a gated clock. a continuous sclk source can only be used if latch is taken high after the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used, and latch must be taken high after the final clock to latch the data. see figure 4 for a timing diagram. readback operation readback mode is invoked by setting the control word and read address as shown in table 9 and table 10 when writing to the input register. the next write to the AD5422 should be a nop command which will clock out the data from the previously addressed register as shown in figure 3. by default the sdo pin is disabled, after having addressed the AD5422 for a read operation, a rising edge on latch will enable the sdo pin in anticipation of data being clocked out, after the data has been clocked out on sdo, a rising edge on latch will disable (tri-state) the sdo pin once again. to read back the data register for example, the following sequence should be implemented: 1. write 0x020001 to the AD5422 input register. this configures the part for read mode with the data register selected. 2. follow this with a second write, a nop condition, 0x000000 during this write, the data from the register is clocked out on the sdo line. table 9. input shift register contents for a read operation msb lsb d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 1 0 x x x x x x x x x x x x x x read address table 10. read address decoding read address function 00 read status register 01 read data register 10 read control register
AD5422 preliminary technical data rev. pre | page 28 of 37 default configuration on initial power-up of the AD5422 the power-on-reset circuit ensures that all registers are loaded with zero-code, as such the default output is the current output with the 4ma to 20ma range selected, the current output until a value is programmed is 0ma. the voltage output pin will be in three-state. an alternative current range or a voltage output range may be selected via the control register. transfer function voltage output for a unipolar voltage output range, the output voltage expression is given by ? ? ? ? ? ? = 2 for a bipolar voltage output range, the output voltage expression is given by 2 2 refin n refin out v gain d gain v v ? ? ? ? ? ? ? = where: d is the decimal equivalent of the code loaded to the dac. n is the bit resolution of the dac. v refin is the reference voltage applied at the refin pin. gain is an internal gain whose value depends on the output range selected by the user as shown in table 11. table 11. output range gain value +5 v 1 +10 v 2 5 v 2 10 v 4 current output for the 0 to 20ma, 0 to 24ma and 4 to 20ma current output ranges the output current expressions are respectively given by d ma i n out ? ? ? ? ? ? = d ma i n out ? ? ? ? ? ? = ma d ma i n out 4 2 16 + ? ? ? ? ? ? = where: d is the decimal equivalent of the code loaded to the dac. n is the bit resolution of the dac.
preliminary technical data AD5422 rev. pre | page 29 of 37 data register the data register is addressed by setting the control word of the input shift register to 0x01. the data to be written to the d ata register is entered in positions d15 to d0 as shown in table 12, table 12. programming the data register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data word control register the control register is addressed by setting the control word of the input shift register to 0x55. the data to be written to th e control register is entered in positions d15 to d0 as shown in table 13. the control register functions are shown in table 14. table 13. programming the control register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clrsel ovrrng rext outen sr clock sr step sren dcen r2 r1 r0 table 14. control register functions option description clrsel see table 20 for a description of the clrsel operation ovrrng setting this bit increases the voltage output range by 10%. further details in features section rext setting this bit selects the external current setting resistor, further details in features section outen output enable. this bit must be set to enable the outputs, the range bits select which output will be functional. sr clock see features section. digital slew rate control sr step see features section. digital slew rate control sren digital slew rate control enable dcen daisychain enable r2,r1,r0 output range select. see table 15 table 15. output range options r2 r1 r0 output range selected 0 0 0 0 to +5v voltage range 0 0 1 0 to 10v voltage range 0 1 0 5v voltage range 0 1 1 10v voltage range 1 0 1 4 to 20 ma current range 1 1 0 0 to 20 ma current range 1 1 1 0 to 24 ma current range reset register the reset register is addressed by setting the control word of the input shift register to 0x56. the data to be written to the reset register is entered in positions d15 to d0 as shown in table 16. the reset register options are shown in table 16 and table 17. table 16. programming the reset register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 reset table 17. reset register functions option description reset setting this bit performs a reset operation, restoring the AD5422 to its initial power on state
AD5422 preliminary technical data rev. pre | page 30 of 37 status register the status register is a read only register. the status register functionality is shown in table 18 and table 19. table 18. decoding the status register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 i out fault slew active over temp table 19. status register functions option description i out fault this bit will be set if a fault is detected on the i out pin. slew active this bit will be set while the output value is slewing (slew rate control enabled) over temp this bit will be set if the AD5422 core temperature exceeds approx. 150c.
preliminary technical data AD5422 rev. pre | page 31 of 37 features fault alert the AD5422 is equipped with a fault pin, this is an open- drain output allowing several AD5422 devices to be connected together to one pull-up resistor for global fault detection. the fault pin is forced active by any one of the following fault scenarios; 1) the voltage at i out attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. the i out current is controlled by a pmos transistor and internal amplifier as shown in figure 58. the internal circuitry that develops the fault output avoids using a comparator with window limits since this would require an actual output error before the fault output becomes active. instead, the signal is generated when the internal amplifier in the output stage has less than approxiamately one volt of remaining drive capability (when the gate of the output pmos transistor nearly reaches ground). thus the fault output activates slightly before the compliance limit is reached. since the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain and an output error does not occur before the fault output becomes active. 2) if the core temperature of the AD5422 exceeds approx. 150c. the open cct and over temp bits of the status register are used in conjunction with the fault pin to inform the user which one of the fault conditions caused the fault pin to be asserted. see table 18 and table 19. voltage output short circuit protection under normal operation the voltage output will sink/source 5ma and maintain specified operation. the maximum current that the voltage output will deliver is 10ma, this is the short circuit current. asynchronous clear (clear) clear is an active high clear that allows the voltage output to be cleared to either zero-scale code or mid-scale code, user- selectable via the clear select pin or the clrsel bit of the control register as described in table 20. (the clear select feature is a logical or function of the clear select pin and the clrsel bit). the current output will clear to the bottom of its programmed range. it is necessary to maintain clear high for a minimum amount of time (see figure 2) to complete the operation. when the clear signal is returned low, the output remains at the cleared value until a new value is programmed. table 20. clear select options clr select output clr value unipolar output range bipolar output range 0 0 v 0 v 1 mid-scale negative full-scale internal reference the AD5422 contains an integrated +5v voltage reference with initial accuracy of 2mv max and a temperature drift coefficient of 10 ppm max. the reference voltage is buffered and externally available for use elsewhere within the system. see figure 56 for a load regulation graph of the integrated reference. external current setting resistor referring to figure 58, r1 is an internal sense resistor as part of the voltage to current conversion circuitry. the stability of the output current over temperature is dependent on the stability of the value of r1. as a method of improving the stability of the output current over temperature an external precision 15k ? low drift resistor can be connected to the r set pin of the AD5422 to be used instead of the internal resistor r1. the external resistor is selected via the control register. see table 13. voltage output over-range an over-range facility is provided on the voltage output. when enabled via the control register, the selected output range will be over-ranged by 10%. digital power supply by default the dv cc pin accepts a power supply of 2.7v to 5.5v, alternatively, via the dv cc select pin an internal 4.5v power supply may be output on the dv cc pin for use as a digital power supply for other devices in the system or as a termination for pull-up resistors. this facility offers the advantage of not having to bring a digital supply across an isolation barrier. the internal power supply is enabled by leaving the dv cc select pin unconnected. to disable the internal supply dv cc select should be tied to 0v. external boost function the addition of an external boost transistor as shown in figure 61 will reduce the power dissipated in the AD5422 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). a discrete npn transistor with a breakdown voltage, bv ceo , greater than 60v can be used. the external boost capability has been developed for those users who may wish to use the AD5422 at the extremes of the supply voltage, load current and temperature range. the boost transistor can also be used to reduce the amount of temperature induced drift in the part. this will minimise the temperature induced drift of the on-chip voltage reference, which improves drift and linearity.
AD5422 preliminary technical data rev. pre | page 32 of 37 boost i out r load AD5422 mjd31c or pbss8110z 1k 0.022 f figure 61. external boost configuration digital slew rate control the slew rate control feature of the AD5422 allows the user to control the rate at which the output value changes. this feature is available on both the current and voltage outputs. with the slew rate control feature disabled the output value will change at a rate limited by the output drive circuitry and the attached load. if the user wishes to reduce the slew rate this can be achieved by enabling the slew rate control feature.with the feature enabled via the sren bit of the control register, (see table 13) the output, instead of slewing directly between two values, will step digitally at a rate defined by two parameters accessible via the control register as shown in table 13. the parameters are sr clock and sr step. sr clock defines the rate at which the digital slew will be updated, e.g. if the selected update rate is 1mhz the output will update every 1s, sr step defines by how much the output value will change at each update. together both parameters define the rate of change of the output value.table 21 and table 22 outline the range of values for both the sr clock and sr step parameters. table 21. slew rate update clock options sr clock update clock frequency (hz) 0000 1000000 0001 500000 0010 333333 0011 250000 0100 200000 0101 100000 0110 50000 0111 33333 1000 25000 1001 20000 1010 12500 1011 10000 1100 8333 1101 6666 1110 5000 1111 3921 table 22. slew rate step size options sr step step size (lsbs) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 the following equation describes the slew rate as a function of the step size, the update clock frequency and the lsb size. 6 10 1 = where: slew rate is expressed in a/s for i out or v/s for v out lsbsize = fullscale range / 65536 when the slew rate control feature is enabled, all output changes will change at the programmed slew rate, i.e. if the clear pin is asserted the output will slew to the clear value at the programmed slew rate. the output can be halted at its current value with a write to the control register. to avoid halting the output slew, the slew active bit can be used to check that the slew has completed before writing to the AD5422 registers. see table 18. i out filtering capacitors two capacitors may be placed between the pins cap1, cap2 and av dd as shown in figure 62. the capacitors form a filter on the current output circuitry reducing the bandwidth and the rate of change of the output current. cap1 cap2 AD5422 av dd i out agnd av dd c 1 c 2 figure 62. i out filtering capacitors
preliminary technical data AD5422 rev. pre | page 33 of 37 applications information driving inductive loads when driving inductive or poorly defined loads connect a 0.01f capacitor between i out and gnd. this will ensure stability with loads beyond 50mh. there is no maximum capacitance limit. the capacitive component of the load may cause slower settling, though this may be masked by the settling time of the AD5422. transient voltage protection the AD5422 contains esd protection diodes which prevent damage from normal handling. the industrial control environment can, however, subject i/o circuits to much higher transients. in order to protect the AD5422 from excessively high voltage transients , external power diodes and a surge current limiting resistor may be required, as shown in figure 63. the constraint on the resistor value is that during normal operation the output level at iout must remain within its voltage compliance limit of av dd C 2.5v and the two protection diodes and resistor must have appropriate power ratings. i out agnd av dd r p r load av dd AD5422 figure 63. output transient voltage protection layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the AD5422 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the AD5422 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the AD5422 should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the AD5422 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce crosstalk between them (not required on a multilayer board that has a separate ground plane, but separating the lines helps). it is essential to minimize noise on the refin line because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feed through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur. the i coupler? family of products from analog devices provides voltage isolation in excess of 2.5 kv. the serial loading structure of the AD5422 make it ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 64 shows a 4-channel isolated interface to the AD5422 using an adum1400 . for further information, visit http://www.analog.com/icouplers. encode decode encode decode encode decode v ia v ib v ic v oa v ob v oc encode decode v id v od adum1400 * controller serial clock out serial data out sync out control out to sclk to sdin to latch to clear *additional pins omitted for clarity figure 64. isolated interface microprocessor interfacing microprocessor interfacing to the AD5422 is via a serial bus that uses protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a latch signal. the AD5422 require a 24-bit data-word with data valid on the rising edge of sclk. for all interfaces, the dac output update is initiated on the rising edge of latch. the contents of the registers can be read using the readback function.
AD5422 preliminary technical data rev. pre | page 34 of 37 thermal and supply considerations the AD5422 is designed to operate at a maximum junction temperature of 125c. it is important that the device is not operated under conditions that will cause the junction temperature to exceed this value . excessive junction temperature can occur if the AD5422 is operated from the maximum av dd and driving the maximum current (24ma) directly to ground. in this case the ambient temperature should be controlled or av dd should be reduced. the conditions will depend on the device package. at maximum ambient temperature of 85c the 24-lead tssop package can dissipate 950mw and the 40-lead lfcsp package can dissipate 1.42w. to ensure the junction temperature does not exceed 125c while driving the maximum current of 24ma directly into ground (also adding an on-chip current of 3ma), av dd should be reduced from the maximum rating to ensure the package is not required to dissipate more power than stated above. see table 23, figure 65 and figure 66. 0 0.5 1 1.5 2 2.5 40 45 50 55 60 65 70 75 80 85 ambient temperature (c) power dissipation (w) tssop lfcsp 25 27 29 31 33 35 37 39 41 43 45 25 35 45 55 65 75 85 ambient temperature (c) supply voltage (v) tssop lfcsp figure 65. maximum power dissipation vs ambient temperature figure 66. maximum supply voltage vs ambient temperature table 23. thermal and supply co nsiderations for each package tssop lfcsp maximum allowed power dissipation when operating at an ambient temperature of 85c mw a t j t 950 42 85 125 ja max = ? = ? w a t j t 42 . 1 28 85 125 ja max = ? = ? maximum allowed ambient temperature when operating from a supply of 60v and driving 24ma directly to ground. ( ) = ? = ? () > ? = ? maximum allowed supply voltage when operating at an ambient temperature of 85c and driving 24ma directly to ground. v ai t t ja dd a j 35 42 027 . 0 85 125 max = ? = ? v ai t t ja dd a j 53 28 027 . 0 85 125 max = ? = ?
preliminary technical data AD5422 rev. pre | page 35 of 37 outline dimensions compliant to jedec standards mo-153-adt 050806-a 24 13 12 1 6.40 bsc 0.15 0.05 0.10 coplanarity top view exposed pad (pins up) bottom view 4.50 4.40 4.30 7.90 7.80 7.70 1.20 max 1.05 1.00 0.80 0.65 bsc 0.30 0.19 seating plane 0.20 0.09 8 0 0.75 0.60 0.45 5.02 5.00 4.95 3.25 3.20 3.15 figure 67. 24-lead thin shrink small ou tline package, exposed pad [tssop_ep] (re-24) dimensions shown in millimeters 1 40 10 11 31 30 21 20 4.25 4.10 sq 3.95 top view 6.00 bsc sq pin 1 indicator 5.75 bcs sq 12 max 0.30 0.23 0.18 0.20 ref seating plane 1.00 0.85 0.80 0.05 max 0.02 nom coplanarity 0.08 0.80 max 0.65 typ 4.50 ref 0.50 0.40 0.30 0.50 bsc pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bot tom view) compliant to jedec standards mo-220-vjjd-2 101306-a figure 68. 40-lead lead frame chip scale package (cp-40) dimensions shown in millimeters ordering guide model temperature range package description package option AD5422brez -40c to 85c 24 lead tssop_ep re-24 AD5422bcpz -40c to 85c 40 lead lfcsp cp-40
AD5422 preliminary technical data rev. pre | page 36 of 37 notes
preliminary technical data AD5422 rev. pre | page 37 of 37 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr06996-0-11/07(pre)

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